1. Field of the Invention
The invention relates to a method of improving the planarization of inter-poly dielectric (IPD) layers, and more particularly to a method of using a rapid thermal process (RTP) to improve the planarization of inter-poly dielectric layers.
2. Description of the Related Art
It is known to use, in very large semiconductor integration (VLSI) circuits, methods which utilize borophosphosilicate glass (BPSG), spin-on-glass (SOG), and etching back techniques to achieve the surface planarization of inter-poly dielectric layers in semiconductor devices.
In a conventional process for fabricating semiconductor devices, on a doped poly-silicon substrate, an undoped inter-poly dielectric layer is formed. Another doped inter-poly dielectric layer is formed on the undoped inter-poly dielectric layer. Being planarized by the above mentioned methods of planarization, a doped poly-silicon layer is formed on the inter-poly dielectric layers. However, it is found that many particles protrude from the interface between the doped inter-poly dielectric layer and the doped poly-silicon. These particles cause an unevenness of the surface, and thus cause serious integration problems, such as the photoresist defocus in the subsequent photolithography process and furnace contamination.